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problems receiving using ethmac
by Unknown on Aug 2, 2007 |
Not available! | ||
Hi,
I've been trying to implement the ethernet core and have been having
problems when I try to generate a packet and send it from my computer
to the FPGA.
The PHY seems to be working okay. Basically at the moment, I can see
incoming data nibbles coming in, carrier sense and receive_data_valid
both go high at the appropriate times, but it appears that nothing is
being done to the incoming data after that. My understanding, which
might not be correct, is that once the packet has been received, the
master cycle and strobe signals should go high while the packet is
being stored to memory, but this is not happening.
I have tried several different configurations of the control
registers, including setting all of them to their default values, with
the one exception of having the RXEN bit enabled in the mode register.
I am fairly sure that the registers are being configured successfully,
because I have been getting acknowledge signals back after configuring
each register.
For reference I am using this board:
http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D25726%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html
Which comes with this PHY:
(http://www.ortodoxism.ro/datasheets2/3/07e8yuswhp32t8yaazrtydfiulyy.pdf)
Any suggestions or insight into the problems I'm having would be
greatly appreciated.
Thanks,
-Danesh
|
problems receiving using ethmac
by rfajardo on Jun 12, 2008 |
rfajardo
Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020 |
||
I don't know if that's the problem Danesh, but as for my understanding
of the MAC controller you shouldn't send layer 4 or else TCP packages
directly to the PHY and more over to the ethmac.
The mac just handles layer 2 protocol and the tcp package is much
larger than the mac one. If you want to receive the right sent data on
your board you should use raw_sockets to get rid of the tcp header or
disable them. At least that's the approach I'm willing to use.
Maybe the mac controller is ignoring the sent packet due to it be too
large. And check the wishbone signals to see if they are also right
for reading. I don't have experience myself yet so that's the best I
can do for you.
Good luck,
Raul
PS: if it works I would really like to know how you did it if you
don't mind.
----- Original Message -----
From: danesh.esteki at gmail.comdanesh.esteki at g...>
To:
Date: Thu Aug 2 19:48:53 CEST 2007
Subject: [ethmac] problems receiving using ethmac
Hi,
http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D25726%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526LID%253D32232%2526PRT%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html
I've been trying to implement the ethernet core and have been having problems when I try to generate a packet and send it from my computer to the FPGA. The PHY seems to be working okay. Basically at the moment, I can see incoming data nibbles coming in, carrier sense and receive_data_valid both go high at the appropriate times, but it appears that nothing is being done to the incoming data after that. My understanding, which might not be correct, is that once the packet has been received, the master cycle and strobe signals should go high while the packet is being stored to memory, but this is not happening. I have tried several different configurations of the control registers, including setting all of them to their default values, with the one exception of having the RXEN bit enabled in the mode register. I am fairly sure that the registers are being configured successfully, because I have been getting acknowledge signals back after configuring each register. For reference I am using this board:
Which comes with this PHY:
(http://www.ortodoxism.ro/datasheets2/3/07e8yuswhp32t8yaazrtydfiulyy.pdf)
Any suggestions or insight into the problems I'm having would be
greatly appreciated. Thanks, -Danesh |
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